An enhanced single gate driven voltage‐balanced SiC MOSFET stack topology suitable for high‐voltage low‐power applications

In the fabrication of some high-voltage low-power applications, low cost is much concerned, and thus using silicon carbide (SiC) MOSFET stack consisting series connected low-voltage devices preferred rather than an expensive single device. Therefore, a cost-efficient gate driven voltage-balanced SiC topology proposed in this paper, where only passive components are equipped with stack. With concept driver, driver design simplified. automatic balancing circuit which operates well sequential lagging good voltage MOSFETs realized without causing extra loss no additional active control required. The working principle illustrated detail parameter selection together consideration presented. Next, compared RCD snubber method delay adjusting to better illustrate its advantages. Finally, typical application, auxiliary power supply, simulation experimental results further verify effectiveness topology.